Prototyping a complex digital integrated circuit is complex and cost-intensive. As a design evolves and is debugged, circuit details may change. Should the design be embodied in an application specific integrated circuit (ASIC), the changes in design require mask changes and also affect related processing steps, thus requiring costly process changes. By prototyping the circuit using a programmable logic device, a user may debug and evolve the design without worrying about related process step changes that would be required if an ASIC were used to implement the design. But the programmability of a programmable logic device (PLD) comes at the cost of larger silicon die area (to provide the programmable features) as compare to an ASIC implementation. Thus, PLDs are often used during the prototyping stage but later replaced by ASICs as the design matures and production volumes increase.
A number of approaches are currently used to convert a design implemented in a PLD into an ASIC. These PLD-to-ASIC conversion processes all typically suffer from a number of problems. For example, although the ASIC will implement the same logic programmed into the PLD, the propagation delays for various signals within the ASIC will differ from the same delays encountered in the PLD. Because the design was optimized for the PLD delays, performance suffers or the ASIC may simply be inoperable. An additional problem is that an ASIC conversion is specific to a given customer's design. To test the ASIC to verify its design during manufacture thus requires customer-provided test vectors. As a result of the burden of having to provide test vectors, the uncertainty of matching propagations delays, and other problems, many users have been reluctant to use an ASIC conversion despite the opportunity to save production costs.
Accordingly, there is a need in the art for improved ASIC conversions for PLDs that will match propagations delays and eliminate the need for customer-provided test vectors.